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奇偶校验电路是一种最小码距为2的一种随机存储器（SRAM）的故障测试方法，实践证明，该方法能够测出的差错占全部存储器差错的97％以上．文章论述了标准INTEL80286计算机的存储器阵列的奇偶校验电路的基本原理；详细地讨论了奇偶校验电路的设计及测试方法．
A parity-check circuit is a random-access memory (SRAM) fault test method with a minimum code length of 2. Practice has proved that this method can detect more than 97% of the total memory errors. This paper discusses the basic principle of the parity circuit of the standard INTEL80286 computer memory array. The design and test methods of the parity circuit are discussed in detail.