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介绍了常用的水平垂直冗余校验码——(7×7)奇偶校验编码解码逻辑电路的EDA设计,用VHDL语言对(7×7)奇偶校验编码器和解码器进行描述,用Quartus II软件进行仿真测试.从仿真结果看,电路完全符合要求,可以烧写成芯片.
This paper introduces the commonly used horizontal and vertical redundancy check code - EDA design of (7 × 7) parity code decoding logic circuit, describes the (7 × 7) parity coder and decoder in VHDL, Quartus II software simulation test from the simulation results, the circuit fully meet the requirements, you can burn into the chip.