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A 4-kbit low-cost one-time programmable(OTP) memory macro for embedded applications is designed and implemented in a 0.18- m standard CMOS process. The area of the proposed 1.5 transistor(1.5T) OTP cell is2.13μm2,which is a 49.3% size reduction compared to the previously reported cells.The 1.5T cellis fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch(HVSW)circuit is also proposed to make sure the OTP macro,implemented in a standard CMOS process,worksreliablywith the high program voltage. The OTP macro is embedded in negative radio frequency identification(RFID) tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600×600μm2. The4-kbit OTP macro only consumes 200×260μm2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.
A 4-kbit low-cost one-time programmable (OTP) memory macro for embedded applications is designed and implemented in a 0.18-m standard CMOS process. The area of the proposed 1.5 transistor (1.5T) OTP cell is 2.1μm2, which is a 49.3% size reduction compared to the previously reported cells. 1.5T cellis fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch (HVSW) circuit is also proposed to make sure the the OTP macro, implemented The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is a standard CMOS process that works reliably with the high program voltage. The OTP macro is embedded in a negative radio frequency identification (RFID) 600 × 600μm2. The4-kbit OTP macro only consumes 200 × 260μm2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.