SFDR相关论文
新公布的数据转换器芯片的调查报告,再一次揭示了芯片性能、集成度和价格方面的种种发展趋势。这份调查报告表明了转换器芯片的当......
An electro-absorption(EA)modulator is one of key components for optical fiber communications due to the high speed,small......
在3月23～28日亚特兰大光纤通信会议上,来自英格兰Bookham技术学院和剑桥大学的研究者描述了直接调制分布反馈激光器的开发情况,这......
引言随着中国开始在人口密集的都市部署第三代(3G)无线业务,各种客观局限性驱使用户对高性能模数转换器(ADC)提出更多重要需求。高......
美国模拟器件公司发布业界首款16 BIT模数转换器(ADC)——AD9446,它具有100 MSPS(每秒兆次采样)数据速率同时提供业界一流的信噪......
引言高速模数转换器(ADC)的性能特性对整个信号处理链路的设计影响巨大。系统设计师在考虑ADC对基带影响的同时,还必须考虑其对射......
An improved structure of linear transconductor is presented in this paper. It is analyzed in theory and simulated with S......
采用高输入频率(IF)的高速模拟一数字变换器(ADC)的系统,其设计一直被证明是一项具有挑战性的任务。而变压器的采用则使得这一任务......
研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器(DDFS).为了减小芯片面积和降低功耗,采用正弦对称技术、mod......
介绍了一个采用改进型1.5位/级结构的10位100MHz流水线结构模数转换器.测试结果表明,模数转换器的信噪失真比最高可以达到57dB,在1......
介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器.这些设计技术包括采用无源电容误差平均来校准电容失配误差、增......
芯片的高性能与低能耗就如同“鱼”与“熊掌”一样难以兼得,这一直是困扰芯片制造商和系统设计师的难题。ADI公司亚太区医疗事业资......
This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter (ADC).A novel mixed-avera......
A fully-differential switched-capacitor sample-and-hold(S/H)circuit used in a 10-bit 50-MS/s pipeline analog-to-digital ......
Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are di......
This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32......
A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input,the sample-and- hold amplifier (SHA) is r......
This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibrati......
AD9650是双通道16位105MSPS、低功耗、低噪声ADC,设计用于医疗成像、工业、频谱分析、多模无线电和雷达应用中的高性能数据采集系......
ADC驱动器为注重时域的仪器仪表应用提供快速压摆率由于电子系统在频率、速度和带宽上的增强,新的技术挑战会限制系统的性能。在过......
Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS pro
Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q~2 random walk NMOS current ......
This paper describes a 10-bit,50-MS/s pipelined A/D converter(ADC) with proposed area- and power-efficient architecture.......
This paper presents a 10-GHz 8-bit direct digital synthesizer(DDS) microwave monolithic integrated circuit implemented i......
This paper describes a 12-bit 40-MS/s and 8-bit 80-MS/s dual-mode low power pipelined analog-to-digital converter (ADC).......
A 1,4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter(ADC) is proposed.Fabricated in the 0.13-μm......
A 10-bit 30-MS/s pipelined analog-to-digital converter(ADC) is presented.For the sake of lower power and area,the pipeli......
An 8-b 100-MS/s pipelined analog-to-digital converter(ADC) is presented.Without the dedicated sample-and -hold amplifier......
A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter(ADC) is presented.This ADC with single track......
提出了一种针对流水线模数转换器(ADC)级间残差放大器的线性增益偏差与增益压缩误差的后台补偿方法.利用随机信号的二阶统计互相关......
This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter (DAC).Analog bac......
A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor ......
This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter(ADC),which is optimized for......
A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert(ADC) is designed for a radio frequency i......
为了获得各个波长独立可调的、稳定的时域交织多波长超短脉冲序列,满足光电混合模数转换器(ADC)对采样脉冲源的需求,该文首次结合......
This paper presents a differential successive approximation register analog-to-digital converter(SAR ADC) with a novel t......
This paper describes a 12-bit,40-MS/s pipelined A/D converter(ADC) which is implemented in 0.18-μm CMOS process drawing......
A 10-bit 2.5 MS/s SAR A/D converter is presented.In the circuit design,an R-C hybrid architecture D/A converter,pseudo-d......
Design of a high performance track and hold (T/H) circuit for high-resolution high-speed analog-to-digital converter (AD......
A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating ana
A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μ......
This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters (ADC).The propos......
An ultra-wideband 4 GS/s 4 bit analog-to-digital converter(ADC)which is fabricated in 2-level interconnect, 1.4μm InGaP......
A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-μm CMOS.An opampsharing MDAC with a switch-embedd......
A 12-bit 30 MSPS pipeline analog-to-digital converter(ADC) implemented in 0.13-μm 1P8M CMOS technology is presented.Low......
A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems
An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter(ADC) is presented.For po......
提出了一种新的光电探测器(PD)非线性模型,进而分析了PD非线性对系统增益及三阶无杂散动态范围(SFDR3)的影响。实验表明,当调制器......
A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is canc......
