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In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60 GHz millimeter wave(mmW) band is designed and implemented in 90 nm CMOS technology. The 60 GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier(LNA) with inter-stage peaking technique, a singlebalanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60 GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60 GHz, supporting four 2.16 GHz receiving channels from IEEE 802.11 ad standard for next generation high speed WiFi applications. Measured results show that the entire receiver achieves a peak gain of 12 dB and an input 1-dB compression point of-14.5dBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60 mA from a 1.2V voltage supply.
In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60 GHz millimeter wave (mmW) band is designed and implemented in 90 nm CMOS technology. The 60 GHz receiver is designed based on the super-heterodyne The proposed 60 GHz receiver frontend derives from the sliding (LNA) with inter-stage peaking technique, a singlebalanced RF mixer, an IF amplifier, and a double-balanced I / Q down- conversion IF mixer. The -IF structure and is designed with 7GHz ultra-wide bandwidth around 60 GHz, supporting four 2.16 GHz receiving channels from IEEE 802.11 ad standard for next generation high speed WiFi applications. Measured results show that the entire receiver achieves a peak gain of 12 dB and an input 1-dB compression point of -14.5 dBm with a noise figure of lower than 7 dB while consuming a total DC current of only 60 mA from a 1.2V voltage supply.