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一、概述微处理器广泛应用对静态RAM的高速、高密集度和低功耗产生了强烈的要求。为了满足这一需求,采用NMOS工艺的16K静态RAM已设计成功。但是在高密集度的RAM中,NMOS增强/耗尽(E/D)电路的功耗问题一直未能完美地解决。这里介绍一个混合CMOS工艺制造的高速8K×8静态RAM。这一工艺就是将CMOS外围电路和NMOS贮存器模片相结合,用此RAM在典型的试验条件下我们得到了34ns的地址存取时间和90mW的有效功率。这里我们采用了带有4个子模块的分方位模片结构和一个新型的读出放大器。除了冗余贮存器单元之处,这个RAM包括
I. Overview Microprocessors are widely used to static RAM high-speed, high density and low power consumption has created a strong demand. To meet this need, 16K static RAM using NMOS technology has been designed successfully. However, in the high-density RAM, the power consumption of the NMOS enhancement / depletion (E / D) circuit has not been solved perfectly. Here to introduce a hybrid CMOS process to create high-speed 8K × 8 static RAM. The process is to combine the CMOS peripheral circuitry with the NMOS memory module, which gives us 34 ns address access time and 90 mW of active power under typical test conditions. Here we use a sub-azimuth die structure with 4 submodules and a new type of sense amplifier. In addition to the redundant memory unit, this RAM is included