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为解决全数字锁相环快速捕获和过滤噪声之间的矛盾,本文提出了一种应用于位同步的具有自动变阶特性的快速高精度超前/滞后全数字销相环(从-DPLL),文中介绍了新的设计思想,重点进行了理论分析,最后给出了有关实验结果。
In order to solve the contradiction between all-digital phase-locked loop fast capture and noise filtering, this paper presents a fast high-precision leading / lagging all digital pin phase-locked loop (from-DPLL) The paper introduces a new design idea, focusing on the theoretical analysis, and finally gives the experimental results.