基于65nm CMOS工艺,设计了一种6.25Gb/s时钟数据恢复电路(CDR)。该CDR采用基于相位插值的双环结构和带有快速锁定算法的2阶积分环路实现,支持半速、全速、倍速3种工作模式。其抖动传输带宽在2~7MHz范围内可调,相位插值精度为2.8°,DNL为1.1°,INL为5.6°。在频差为1.0×10-3时,其锁定速度较传统CDR提高了1倍以上,可应用于满足PCI-E、RAPIDIO协议、短期爆发性传输数据的高速串行接口领域。 Based on the 65nm CMOS process, a 6.25Gb / s clock data recovery circuit (CDR) is designed. The CDR is based on a two-loop phase-interleaved architecture and a 2-order integral loop with a fast-lock algorithm. It supports three operating modes: half speed, full speed and double speed. Its jitter transfer bandwidth is adjustable from 2MHz to 7MHz with phase interpolation accuracy of 2.8 °, DNL of 1.1 ° and INL of 5.6 °. When the frequency difference is 1.0 × 10-3, the locking speed is more than double than that of the traditional CDR, and it can be applied in the field of high speed serial interface that meets PCI-E, RAPIDIO protocol and short-term burst data transmission.