通过数值模拟手段 ,用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对 R- G电流大小的影响规律 .结果表明 :无论在 FD还是在 PD SOI MOS器件中 ,界面陷阱密度是决定 R- G电流峰值的主要因素 ,硅膜厚度和沟道掺杂浓度的影响却因器件的类型而异 .为了精确地用 R- G电流峰值确定界面陷阱的大小 ,器件参数的影响也必须包括在模型之中 The effects of interface traps, silicon film thickness and channel doping concentration on R-G current were studied by means of numerical simulation. The results show that, in FD or PD SOI MOS devices, the interface The trap density is a major factor in determining the R-G current peak, and the effect of the thickness of the silicon film and the doping concentration of the channel varies depending on the type of the device. In order to accurately determine the size of the interface trap with the R-G current peak, The impact must also be included in the model