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为了在不降低快速响应热释电探测器响应速度的同时抑制器件的振动干扰,通过对快速响应热释电红外探测器的振动噪声机理和输出电信号的频谱分析,提出了数字降噪方案,并用基于FPGA的硬件电路来实现。文中还介绍了硬件的结构和FPGA代码实现,给出了降噪之后的实际效果。
In order to suppress the vibration interference of the device without reducing the response speed of the rapid response pyroelectric detector, a digital noise reduction scheme is proposed by analyzing the vibration noise mechanism of the rapid response pyroelectric infrared detector and the spectrum analysis of the output electrical signal, And using FPGA-based hardware circuit to achieve. The paper also introduced the hardware structure and FPGA code implementation, gives the actual effect after noise reduction.