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介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择。采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗。同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路。采用SMIC0.13μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm。测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 d B,信噪失真比(SNDR)为55.7 d B,ADC的品质因子(Fo M)为1.07 p J/conv.,而功耗为107 m W。
A 12 bit 200 MS / s A / D converter (ADC) for wireless transceivers is introduced. Pipelined analog-to-digital converters are typical architectures with high-frequency sampling from mid-frequency to high-frequency sampling. The idea of combining multiple pipelined analog-to-digital converters into an analog-to-digital converter using time-interleaving techniques is a complex structure and energy utilization A compromise between rates. Using techniques such as time interleaving, pipelining, and op amp sharing, both speed and accuracy are improved, while power consumption is saved. Meanwhile, in order to reduce the influence of timing mismatch on the ADC performance of the time-interleaved pipeline, a sample-and-hold circuit insensitive to timing distortion is proposed. The circuit design is carried out with SMIC0.13μm CMOS technology, the core circuit area is 1.6mm × 1.3mm. The test results show that the SFDR can reach 67.8 dB with a SNDR of 55.7 dB at a sampling rate of 200 MS / s and an analog input signal frequency of 1 MHz. The ADC’s The quality factor (Fo M) is 1.07 p J / conv. While the power dissipation is 107 mW.