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本文从几个方面探讨了一种应用粘合二氧化硅片制作绝缘体上硅的新技术。粘合是通过将一对亲水表面相互贴合的硅片置于惰性气体中加热来实现的。提出了一种以裂解传播理论为基础的适用于计算粘合表面能的定量方法。研究发现粘合强度随着粘合温度的升高而增加,从室温下的60～85尔格/cm~2升到1400℃时的2 200尔格/cm~2。粘合强度基本上与键合时间无关。通过800℃退火10分钟达到的机械强度,足以承受为获得所需厚度而对上面硅片进行的机械或化学减薄加工以及随后的器件制作工序。提出了一种模型解释在实验温度范围内粘合的三种明显状态。采用金属-氧化物-半导体(MOS)电容器来测试粘合的电特性,其结果与在粘合界面处的负电行密度约10~(11)cm~(-2)一致。采用两次深腐蚀工艺将芯片低薄到希望的厚度,其厚度均匀性在 4英寸硅片上为± 20nm。剩余硅层中的线位错密度是10~2～10~3cm~(-2),残留的掺杂剂浓度少于5×10~(15)cm~(-3),两者都是腐蚀阻挡层的剩余物。在20～100mm厚的硅层上制作的互补金属-氧化物-半导体(CMOS)器件具有 60mV/dec亚阈值斜率(包括n沟和p沟MOS晶体管)。有效载流子寿命在80nm和300nm厚硅膜中是15～20μs。在硅膜覆盖的氧化层界面上的界面态密度是≥5 ×10~(10)cm(-2)。
In this paper, a new technique of making silicon on insulator using bonded silica sheet is discussed from several aspects. Bonding is achieved by placing a pair of silicon wafers, which have a hydrophilic surface in contact with each other, in an inert gas atmosphere. A quantitative method based on the theory of crack propagation is proposed to calculate the bonding surface energy. It was found that the bonding strength increased with the increase of the bonding temperature, ranging from 60 to 85 erg / cm 2 at room temperature to 2 200 erg / cm 2 at 1400 ° C. The bonding strength is basically independent of the bonding time. The mechanical strength reached by annealing at 800 ° C for 10 minutes is sufficient to withstand the mechanical or chemical reduction of the upper silicon wafer to obtain the desired thickness and subsequent device fabrication processes. A model is presented to explain three distinct states of adhesion within the experimental temperature range. Metal-oxide-semiconductor (MOS) capacitors were used to test the electrical properties of the bond, the result of which is consistent with a negative charge density of about 10-11 cm -2 at the bond interface. The chip is thinned to the desired thickness using two deep etch processes with a thickness uniformity of ± 20 nm on a 4 inch wafer. The remaining dislocations concentration is less than 5 × 10 ~ (15) cm ~ (-3), both of which are corrosive The remainder of the barrier. Complementary metal-oxide-semiconductor (CMOS) devices fabricated on 20-100 mm thick silicon layers have sub-threshold slopes of 60 mV / dec, including n-channel and p-channel MOS transistors. The effective carrier lifetime is 15-20 μs in 80 nm and 300 nm thick silicon films. The interface state density is ≥5 × 10 ~ (10) cm (-2) at the silicon oxide covered oxide layer interface.