Power is the major challenge threatening the progress of very large scale integration (VLSI) tech-nology development. In ultra-deep submicron VLSI designs,clock network size must be minimized to re-duce power consumption,power supply noise,and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations,register placement actu-ally strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result,incremental modifications are per-formed based on the clock skew specifications by moving registers toward preferred locations that may re-duce the clock network size. At the same time,the side-effects to logic cell placement,such as signal net wirelength and critical path delay,are controlled. Test results on benchmark circuits show that the methodol-ogy can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay. Power is the major challenge threatening the progress of very large scale integration (VLSI) tech-nology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to re-duce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actu-ally strongly influences the clock network size. network design methodology that optimizes register placement. incremental modifications are per-formed based on the clock skew specifications by moving registers toward preferred locations that may re-duce the clock network size. At the same time, the side -effects to logic cell placement, such as signal net wire length and critical path delay, are controlled. Test results on bench mark circuits show that the methodol-ogy can reduce reduce clock network size with limited impact on signal net wirelength and critical path delay.