论文部分内容阅读
介绍一组基于0.18μm逻辑平台构建的低导通态电阻(Low Ron)NLDMOS。该组LDMOS涵盖10~30 V应用电压。该NLDMOS为完全隔离型,因而其源端和漏端均可以独立于衬底加偏压。针对Drift区域和Body区域分别进行结构优化,最终得到性能良好的低导通态电阻(Low Ron)NLDMOS。其导通态电阻(Ron)为4.4 mΩ·mm-2对应击穿电压(BV)~20 V,21 mΩ·mm-2对应击穿电压(BV)~41 V。
Introducing a set of Low Ron NLDMOS based on a 0.18μm logic platform. The group LDMOS covers 10 ~ 30 V application voltage. The NLDMOS is fully isolated, so both its source and drain can be biased independently of the substrate. Structural optimization is performed for the Drift and Body regions, respectively, resulting in a well-behaved Low Ron NLDMOS. The on-state resistance (Ron) of 4.4 mΩ · mm-2 corresponds to a breakdown voltage (BV) of ~ 20 V and a 21 mΩ · mm-2 corresponds to a breakdown voltage (BV) of ~ 41 V.