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TRW电子公司加里福尼亚Redondo Beach实验室研制出空用计算机系统用的射极跟随器逻辑(EFL)64位并行相关器,并已交付使用。这种部件的基片面积为220×230平方密耳,包含5000个器件;工作频率为20兆赫。另外,TRW公司利用三次扩散形成EFL的方法制成单块16×16位并行乘法器,其基片面积为301X279平方密耳,包含不少于16700个双极器件(相当于3000多个门)。使EFL逻辑成为实现新的逻辑范畴(超大规模集成——VLSI)的途径之一。在16位,6MHz的计算机中决定采用这种片式乘法器。军用和空用计算机将用10片组成,其中4片是VLSI。它的指令脉冲持续时间为400～800毫微秒,向小型化迈进了一步。但是EFL不是唯一的发展中的双极LSI。几乎一年前就有了125个门的肖特基TTL累加器〔Elec-tronics, Aug. 30, 1973, P. 263〕,而集成度达1000个等效门的单片肖特基控制器也即将问世。世界各国都计划利用集成度达1000-3000个门的集成注入逻辑(I~2L)技术来设计用在中心信息处理机、仪器和手表中的LSI电路〔Electronics, Sept. 13, 1973, P. 35〕。
Redondo Beach, California, a TRW electronics company, has developed an emitter-follower logic (EFL) 64-bit parallel correlator for use in computer systems and is shipping. The substrate area of this part is 220 × 230 square mil and contains 5000 devices; the operating frequency is 20 MHz. In addition, TRW uses triple diffusion to form EFLs to make a single 16 × 16-bit parallel multiplier with a substrate area of 301 × 279 square mil and a minimum of 16,700 bipolar devices (equivalent to more than 3,000 gates) . Make EFL logic one of the ways to implement the new logical category (Very Large Scale Integration - VLSI). In the 16-bit, 6MHz computer decided to use this chip multiplier. Military and empty computers will be made up of 10 pieces, four of which are VLSI. Its command pulse duration is 400 to 800 nanoseconds, a step toward miniaturization. But EFL is not the only developing bipolar LSI. A Schottky TTL accumulator with 125 gates almost a year ago [Electronics, Aug. 30, 1973, p. 263], while a monolithic Schottky controller with 1000 gates of integration Also coming soon. Countries all over the world plan to design LSI circuits for use in central processors, instruments and watches using Integrated I-2L technology with integration of 1000-3000 gates [Electronics, Sept. 13, 1973, p. 35].