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This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication.By splitting the direct current through conventional cascode topology,the constraint of stacking-MOS structure for supply voltage has been removed and based on forward-body-bias technology,the circuit can operate at 0.5 V supply voltage.Design details and RF characteristics have been investigated in this paper.To verify the investigation,a 0.5 V 5.4 GHz LNA has been fabricated through 0.18μm CMOS technology and measured. Measured results show that it obtains 9.1 dB gain,3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm.Compared with previously published cascode LNA,it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.
This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking-MOS structure for supply voltage has been removed and based on forward-body- bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 μm CMOS technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.