为了研究寄存器级硬件描述语言在RISC型微处理机结构设计方面的应用,我们使用寄存器级硬件描述语言ERES对微处理机RISC Ⅱ进行了描述。建立了一个RISCⅡ的模拟器。ERES语言是非过程性描述语言,带有精确的时间描述,特别适合于描述微处理机结构。通过这项工作,我们认为ERES语言在RISC型微处理机结构设计方面有以下几个作用(1)对于研究体系结构提供帮助;(2)可以建立指令模拟器;(3)对数据通路,控制通路进行验证;(4)检验所设计结构的效率。 In order to study the application of register-level hardware description language in the structural design of RISC type microprocessors, we describe the microprocessor RISC II using register-level hardware description language ERES. Established a RISC Ⅱ simulator. The ERES language is a non-procedural description language with an accurate description of the time and is ideally suited to describing the microprocessor architecture. Through this work, we think ERES language has several functions in RISC microprocessor structure design. (1) It is helpful to research architecture. (2) Instruction emulator can be set up. (3) Data path, control Path to verify; (4) test the efficiency of the design structure.