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本文的目的是介绍一种在500兆赫下能输出50瓦功率,功率增益为10分贝,效率为50％的晶体管。工艺与封装设计的改进是采用复盖技术和双基极集成引线的几何图形。采用新的电路技术进行器件试验并提供下述结果:在500兆赫下输出功率为39瓦,功率增益为5.1分贝,集电极效率为70％。在400兆赫下输出功率43瓦,功率增益为4.9分贝,集电极效应为81％。所有试验被限定在400兆赫下进行,这是因为器件使用在这个频率。最后的集电极效率远远超过规定。在400兆赫下脉冲功率达到70瓦。负载失配试验的结果表明,该器件能容许在400兆赫下电压驻波比为25:1,而性能没有损坏。相互调制的失真度在输出为40瓦时是—30分贝。总共提供了132支成品管子。
The purpose of this article is to introduce a transistor capable of delivering 50 watts at 500 MHz with a power gain of 10 dB and an efficiency of 50%. Process and package design improvements are made using overlay technology and dual-base integrated lead geometries. Device testing was performed using new circuit technology and provided the following results: 39 Watts output power at 500 MHz, 5.1 dB power gain, and 70% collector efficiency. The output power was 43 watts at 400 MHz, the power gain was 4.9 dB, and the collector effect was 81%. All tests were limited to 400 MHz, because the device is used at this frequency. The final collector efficiency far exceeds the regulation. The pulse power reaches 70 W at 400 MHz. The results of the load mismatch test show that the device can tolerate a 25: 1 VSWR at 400 MHz with no performance degradation. The intermodulation distortion is -30 dB at 40 W output. A total of 132 finished tubes were provided.