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提出实现VLSI的PSSWS(Poly Silicon Side Wall Spacer)—LDD(Lightly DopedDrain)结构,研究了它的形成工艺,获得多晶侧壁形成的优化工艺条件,制作出亚微米有效沟道长度的LDD NMOSFET。在器件性能研究和计算机模拟的基础上,得到PSSWS—LDDMOSFET的优化工艺实现条件;此条件下实现的有效沟道长为0.8μm的PSSWS—LDDNMOSFET,源漏击穿电压达20V,常规器件的小于16V;衬底电流较常规器件的减小约二个数量级。利用此优化条件,研制出高性能的1μm沟道长度的CMOS CD4007电路,2μm沟道长的21级CMOS环振,LSI CMOS 2.5μm沟道长度的门阵列电路GA 300 5SD。结果表明:PSSWS—LDD MOSFET性能衰退小,速度快,可靠性高,适用于VLSI的制造。
The PSSWS (Lightly Doped Drain) structure of VLSI is proposed. The formation process of the PSSWS (LDS) is studied. The optimal process conditions for the formation of polycrystalline sidewalls are obtained and the LDD NMOSFET with sub-micron effective channel length is fabricated. Based on the research of device performance and computer simulation, the optimal process conditions of PSSWS-LDDMOSFET are obtained. The effective channel length of PSSWS-LDDNMOSFET with 0.8μm channel length is achieved. The breakdown voltage of source and drain is up to 20V. 16V; substrate current reduction of conventional devices about two orders of magnitude. With this optimized condition, a CMOS CD4007 circuit with 1μm channel length, a GAO-2 CMOS gate array with 2μm channel length and a CMOS CMOS gate array with 2.5μm channel length was developed. The results show that: PSSWS-LDD MOSFET performance decline, fast, high reliability, suitable for VLSI manufacturing.