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For 3D vertical N AND flash memory,the charge pump output load is much larger than that of the planar NAND.resulting in the performance degradation of the conventional Dickson charge pump.Therefore,a novel all PMOS charge pump with high voltage boosting efficiency,large driving capability and high power efficiency for3 D V-NAND has been proposed.In this circuit,the Pelliconi structure is used to enhance the driving capability,two auxiliary substrate bias PMOS transistors are added to mitigate the body effect,and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure.Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86%and power efficiency of 50%.The output voltage of the proposed 9 stages charge pump can exceed 2 V under2 MHz clock frequency in 2X nm 3D V-NAND technology.Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.
For 3D vertical N AND flash memory, the charge pump output load is much larger than that of the planar NAND. Resulting in the performance degradation of the conventional Dickson charge pump. Before, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3 D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop was eliminated by dynamic gate control structure. Simulation results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high den sity 3D V-NAND integration.