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基于Cadence公司Encounter数字技术开发出55纳米平台的参考设计流程日前,全球电子设计创新领先企业Cadence设计系统公司与上海华力微电子有限公司共同宣布华力微电子基于Cadence誖Encounter誖数字技术交付出55纳米平台的参考设计流程。从现在起,华力微电子首次在其已建立的55纳米工艺平台上实现了从RTL到GDSII的完整流程。在该流程中所使用的Cadence数字工具包括RTL Compiler、Encounter Digital Implementation系统、Conformal LEC、QRC Extraction、Encounter Timing系统、Encounter Power系统和Physical Verification系统。除了Cadence工具以
A 55-nm platform reference design process based on Cadence’s Encounter digital technology Cadence Design Systems, a global leader in electronic design innovation, and Shanghai Huali Microelectronics Co., Ltd. jointly announced that Huali Microelectronics delivered a Cadence-based Encounter paradox digital technology 55 nm platform reference design flow. From now on, for the first time, Huali Microelectronics has implemented the complete flow from RTL to GDSII on its established 55nm process platform. Cadence digital tools used in this process include RTL Compiler, Encounter Digital Implementation System, Conformal LEC, QRC Extraction, Encounter Timing System, Encounter Power System and Physical Verification System. In addition to Cadence tools