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基于上海微系统与信息技术研究所0.13μm抗辐射部分耗尽(PD)绝缘体上硅(SOI)互补金属氧化物半导体(CMOS)工艺标准单元库,设计了一款测试芯片,针对总剂量辐射效应对抗辐射标准单元库的验证方法进行研究。测试芯片主要用于测试标准单元的功能和性能,同时为了满足总剂量辐射测试的试验要求,开发了现场可编程门阵列(FPGA)自动测试平台,用于芯片测试和数据采集工作。试验在模拟空间辐射环境下进行,通过了总剂量150 krad(Si)的辐射测试。测试经过辐射后的芯片,单元功能保持正确,性能变化在10%以内,经过退火处理后,内核(core)电流恢复辐射前的水平。
A test chip was designed based on the 0.13μm radiation-resistant partially-depleted (PD) SOI CMOS cell library of Shanghai Institute of Microsystem and Information Technology. Aiming at the effect of total dose radiation effect Research on the verification method of radiation standard cell library. The test chip is mainly used to test the function and performance of the standard cell. Meanwhile, in order to meet the test requirements of the total dose radiation test, a field programmable gate array (FPGA) automatic test platform has been developed for chip testing and data acquisition. The test was conducted in a simulated space radiation environment and passed a total radiation dose of 150 krad (Si). Test the radiation after the chip, the unit function is maintained correctly, the performance changes in less than 10%, after annealing treatment, the core (core) current recovery before radiation levels.