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基于软判决译码规则,采用完全并行的解码结构,使用Verilog硬件描述语言,在Xilinx公司的FPGA(Virtex-2 xcv 1000)上实现了码率为1/2、帧长为20bit的规则(3,)LDPC码的译码器,最大传输速率可达20Mbps。对LDPC码的实际应用具有重要的推动作用。
Based on the soft-decision decoding rules, a completely parallel decoding structure is implemented by using the Verilog hardware description language. The Xilinx FPGA (Virtex-2 xcv 1000) has a code rate of 1/2 and a frame length of 20 bits ,) LDPC code decoder, the maximum transfer rate up to 20Mbps. The practical application of LDPC code has an important role in promoting.