某些逻辑电路需要用恒值信号电平来显示某一点所出现的脉冲,并且检测该恒值信号以确定有无脉、冲。如图1所示,多谐振荡器与延迟线的组合电路,当 A 点出现周期重复的输入脉冲时,在其1点将有负的恒值电平。如果脉冲链中断,1点输出将触发为“0”。该电路设计成在静止时 A 点处于地电位。如果有负脉冲链出现,第一个脉冲将触发多谐振荡器,并在 Some logic circuits need to use a constant signal level to display the pulse at a certain point, and detect the constant signal to determine whether there is pulse or not. As shown in Figure 1, multivibrator and delay line combination circuit, when there is a periodic repetitive input pulse at point A, there will be a negative constant level at its 1 point. If the pulse train is interrupted, 1 output will trigger “0”. The circuit is designed to be at ground potential at point A at rest. If there is a negative pulse chain, the first pulse will trigger the multivibrator and on