论文部分内容阅读
引言集成逻辑电路制造技术的不断改进,起初着手于旨在较短延迟时间方面的成就。然而到1970年前后,速度可能提高的程度事实上已达到某种极限,因而现在的趋势是朝着提高每块芯片上门电路数目的方向发展。对于希望象单个单元那样制作多门电路的一些应用来说,这种大规模集成(LSI)的形式将构成一种改进。如要LSI 能成为一种切实可行的建议,逻辑电路就必须满足三个重要条件。首先,基本“积木式单元”(buildingblocks)必须有简单而紧凑的结构,以便将尽可能多的单元容纳在单块芯片上。其次,应按速度适当且芯片功耗不过大的原则设计电路,这就意味着门延时τ与门功耗D 之乘积τD(这一要求的测定因数)必须足够小,第三,制造
INTRODUCTION The continuous improvement of integrated logic circuit manufacturing technology began with efforts aimed at shorter latency. However, by the 1970s, the extent to which speed might have risen had actually reached a certain limit, and the trend is toward increasing the number of on-chip circuits per chip. For some applications that wish to make multiple gates as a single cell, this form of LSI will make an improvement. To make LSI a viable proposal, logic must meet three important conditions. First, the basic “building blocks” must have a simple and compact structure to accommodate as many cells as possible on a single chip. Secondly, the circuit should be designed according to the principle of appropriate speed and the chip power dissipation, which means that the product of the gate delay τ and the gate power consumption τD (the determination factor of this requirement) must be small enough. Thirdly,