论文部分内容阅读
针对电荷泵锁相环的抖动问题,对CMOS电荷泵锁相环的压控振荡器电路进行改进;设计了一种采用增益补偿技术的压控振荡器,实现了可用于DC-DC变换器中与外部时钟同步的电荷泵锁相环。电路设计基于TSMC 0.18μm CMOS工艺,采用HSPICE软件仿真验证。仿真结果表明,在3.3 V电源电压-、40℃~85℃温度范围内,该电荷泵锁相环能够与外部时钟同步于1.5~3.5 MHz的频率范围,锁定时间小于72μs,功耗小于1.3 mW。
Aiming at the jitter problem of the charge pump PLL, the voltage-controlled oscillator circuit of the CMOS charge pump PLL is improved. A voltage-controlled oscillator with gain compensation technology is designed, which can be used in DC-DC converter Charge pump phase locked loop synchronized with external clock. The circuit design is based on TSMC 0.18μm CMOS technology, using HSPICE simulation software. The simulation results show that the charge pump PLL can synchronize with the external clock in the frequency range of 1.5 ~ 3.5 MHz with a lock time of less than 72 μs and a power consumption of less than 1.3 mW at a supply voltage of 3.3 V, -40 ° C to 85 ° C .