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提出了同时考虑通孔效应和边缘传热效应的互连线温度分布模型,获得了适用于单层互连线和多层互连线温度分布的解析模型,并基于65nm互补金属氧化物半导体(CMOS)工艺参数计算了不同长度单层互连线和多层互连线的温度分布.对于单层互连线,考虑通孔效应后中低层互连线的温升非常低,而全局互连线几乎不受通孔效应的影响,温升仍然很高.对于多层互连线,最上层互连线的温升最高,温升和互连介质层厚度近似成正比,而且互连介质材料热导率越低,温升越高.所提出的互连线温度分布模型,能应用于纳米级CMOS计算机辅助设计.
An interconnection temperature distribution model considering both the through-hole effect and the edge heat transfer effect is proposed. An analytical model suitable for the temperature distribution of single-layer interconnect lines and multi-layer interconnection lines is obtained. Based on the temperature distribution model of 65nm CMOS (Complementary Metal Oxide Semiconductor) CMOS) process parameters to calculate the temperature distribution of different lengths of single-layer interconnect lines and multi-layer interconnect lines.For single-level interconnect lines, taking into account the through-hole effects of low-level interconnect temperature rise is very low, and the global interconnect The line is hardly affected by the through-hole effect, and the temperature rise is still still high.For multilayer interconnect lines, the temperature rise of the top interconnect is the highest, and the temperature rise is approximately proportional to the thickness of the interconnect dielectric layer, and the interconnection dielectric material The lower the thermal conductivity, the higher the temperature rise.The proposed interconnection temperature distribution model can be applied to nanometer CMOS computer-aided design.