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图1中的电路是一个边沿触发的单稳电路,它基于以前一个边沿触发的抛物线脉冲发生器设计(参考文献1)。本电路对早期的发生器做了一个简单但大幅的改动,即将由级联积分器第一级的S2与IC3(见原设计)组成的输入端与基准电压源VREF断开,而将其连接到图1中的输入电压端子。EQUATION1
The circuit in Figure 1 is an edge-triggered monostable circuit based on the design of a parabolic pulse generator triggered by a previous edge (Reference 1). This circuit made a simple but drastic change to the early generators by disconnecting the input consisting of the S2 and IC3 (see original design) of the first stage of the cascaded integrator from the reference VREF and connecting it To the input voltage terminal in Figure 1. EQUATION1