在设计以Z80CPU为基础的系统时,常会遇到这样的问题,即如何支持Z80系列器件所要求的特定电平时钟输入。按设计手册中规定的时钟高输入电平电压为Vcc—0.6V,这超出了所有标准TTL逻辑高电平要求的范围。在过去,为产生一适当的时钟,则采用一晶体管驱动电路来上拉时钟电平。但这些方案适合于复杂的系统设计中。 When designing a system based on the Z80CPU, you often encounter the problem of how to support the specific level clock inputs required by the Z80 family of devices. The high input voltage level of the clock as specified in the design manual is Vcc-0.6V, which is outside the range required by all standard TTL logic highs. In the past, to generate a proper clock, a transistor driver circuit was used to pull up the clock level. However, these solutions are suitable for complex system design.