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该文提出一种应用于全数字锁相环高分辨率的时间数字转换器TDC。该TDC延时单元由两级特殊的反相器构成,其中第一个反相器只考虑上升沿,而第二个反相器只考虑下降沿,通过合理选择两级反相器的尺寸可使总延时小于传统延时单元的一半,从而提高了TDC的分辨率。针对这种只考虑单沿的延时单元,该文还提出了相应的TDC系统。实验结果表明,在0.18μm CMOS工艺下,该文提出TDC的分辨率能达到28 ps。
This paper presents a digital time-to-digital converter TDC for all-digital phase-locked loop high-resolution. The TDC delay unit consists of two special inverters, of which the first inverter only considers the rising edge, and the second inverter only considers the falling edge. By reasonably choosing the size of the two-stage inverter The total delay is less than half of the traditional delay unit, thereby increasing the resolution of TDC. For this delay unit which only considers a single edge, this paper also proposes the corresponding TDC system. Experimental results show that under the 0.18μm CMOS process, the proposed TDC resolution can reach 28 ps.