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采用WN栅自对准GaAs MESFET工艺成功地制造出2k门DCFL GaAs门阵列。芯片尺寸为4.59mm×4.73mm。基本单元由一个耗尽型FET(DFET)和三个增强型FET(EFET)构成。通过专用的第一、第二层互联和接触孔掩膜,可以构成反相器,或者一个2或3输入端的或非门。I/O缓冲级设计为一个大尺寸的DCFL推挽电路。功率耗散为0.5mW/门时,空载延迟时间为42ps/门,由于各种负载电容而使延迟时间的增量为:11ps/扇入,16ps/扇出,59ps/1mm互联线和0.95ps/交迭点(面积为2μm×3μm)。在这个门阵列芯片上已制造出8×8位并行乘法器。包括I/O缓冲级,功率耗散约为400mW时,乘法时间达到8.5ns。
A 2k-gate DCFL GaAs gate array was successfully fabricated using a WN gate self-aligned GaAs MESFET process. The chip size is 4.59mm × 4.73mm. The basic unit consists of a depletion-mode FET (DFET) and three enhancement-mode FETs (EFETs). Through dedicated first and second layers of interconnects and contact hole masks, an inverter or a 2 or 3-input NOR gate can be constructed. The I / O buffer is designed as a large DCFL push-pull circuit. Power Dissipation is 0.5mW / gate, no-load delay time of 42ps / gate, due to a variety of load capacitance delay time increment: 11ps / fan in, 16ps / fanout, 59ps / 1mm interconnect and 0.95 ps / crossover point (area 2 μm × 3 μm). An 8 × 8-bit parallel multiplier has been fabricated on this gate array chip. Including the I / O buffer stage, the power dissipation of about 400mW, the multiplication time of 8.5ns.