文章针对高k栅MOSFET的栅介质层及其侧壁掩蔽层提出了一个二维定解问题,求出了二维电势和电荷分布.文章根据栅极电荷与栅源及栅漏电压关系,提出了MOSFET的栅极和源极/漏极之间的寄生电容的模型,用半解析法计算了这些寄生电容,得到了寄生电容与几何尺寸之间的关系.文章的计算结果表明改变栅极电介质常数可以得到一个寄生电容的最小值,计算结果与CST仿真结果能够很好地符合. This paper presents a two-dimensional solution to the gate dielectric layer and its sidewall masking layer of a high-k gate MOSFET and obtains the two-dimensional potential and charge distribution. According to the relationship between gate charge and gate-source and gate-drain voltage, The model of parasitic capacitance between MOSFET gate and source / drain is calculated and the parasitic capacitances are calculated by semi-analytical method, and the relationship between parasitic capacitance and geometrical size is obtained.The calculation results show that the gate dielectric The constant can get the minimum value of a parasitic capacitance, and the calculation result can well accord with the CST simulation result.