Automated Design Space Exploration of Transient Fault Detectable Datapath Based on User Specified Po

来源 :2015 International Symposium on VLSI Design, Automation and | 被引量 : 0次 | 上传用户:jinmin511
下载到本地 , 更方便阅读
声明 : 本文档内容版权归属内容提供方 , 如果您对本文有版权争议 , 可与客服联系进行内容授权或下架
论文部分内容阅读
A novel automated design space exploration (DSE) approach of multi-cycle transient fault detectable datapath based on multi-objective user constraints (power and delay) during high level synthesis (HLS) is presented in this paper.
其他文献
This paper presents the design of a variable gain amplifier for the application to the frontend circuitry of 5-GHz high-speed digital storage oscilloscopes.
会议
In this paper,we propose a hybrid built-in selftest BIST scheme for DRAMs.The hybrid BIST consists of a microcode-based controller for supporting the programmability of test algorithms and an FSM-base
会议
Hybrid scrambling technique is proposed for NROM-based ROMs in order to enhance the fabrication yield and reliability in this paper.Besides the traditional hardware redundancy techniques,fault masking
会议
The K-Best algorithm for MIMO detections has been widely used in wireless communication systems.In this paper,to increase the throughput cost-effectively,two novel computational schemes are applied to
会议
For miniaturized multi-gas sensors,the detected multi-gas signals would be self-interfered by responses to multiple gases.In this paper,a fast Independent Component Analysis FICA is proposed to restor
会议
In this paper,an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique.
会议
Many current source models CSMs have been proposed for the gate-level circuit analysis and timing analysis for sub-90-nm CMOS designs during the past decade.
会议
The ever-increasing transistor threshold-voltage Vth variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells.To keep power limitations,scaling down
会议
For the last decade,there have been varying techniques for hardware prefetching to improve the system performance.However,untimely prefetching may pollution caches and resulting into significant perfo
会议
Voltage-frequency island VFI -based design has been widely exploited for optimizing system energy of embedded multi-core chip in recent years.
会议