在采用基于VelociTI结构浮点DSPs流水线模式设计具有自主知识产权的数字信号处理器中,为了正确有效地实现对流水线异常的控制,提出了一种该结构流水线发生异常时的处理方法。对引起流水线异常的情况进行了合理的分类,存储器阻塞、多执行包和多周期NOP指令采用通过控制流水线寄存器的时钟信号实现控制。采用控制指令的执行条件实现了中断引起的流水线队列中部分指令的废除。对提出的方法采用VHDL语言建模设计,仿真结果验证了其正确性。 In the digital signal processor with independent intellectual property rights based on the VelociTI floating-point DSPs pipelining design, in order to control the abnormality of the pipeline correctly and effectively, a method of processing when the pipeline of the structure is abnormal is proposed. A reasonable classification of pipeline anomalies is made, with memory blocking, multi-execution packs, and multi-cycle NOP instructions controlled by the clock signal through the control pipeline registers. Adopting the execution condition of the control instruction realizes the abolition of some instructions in the pipeline caused by the interrupt. The proposed method uses VHDL language modeling and design, the simulation results verify its correctness.