文章介绍了一种利用CPLD进行数字钟设计的方法,设计中采用VHDL语言进行每个模块程序的设计,实现利用数码管进行时、分、秒的显示,利用按键进行时间的设置与调整,并且在CPLD实验板上进行了验证,实现了系统的设计。本设计采用模块化设计,具有设计简单,程序可读性强等特点。 This paper introduces a method of using CPLD digital clock design, the design of VHDL language for each module program design, the use of digital control for hours, minutes, seconds display, the use of keys to set the time and adjust, and In the CPLD experimental board was verified to achieve the system design. The design uses a modular design, with a simple design, program readability and other characteristics.