本文讲述了降低磁芯存贮器耗功的有关问题。分析了磁芯存贮器耗功的分布情况。在存取周期不快的磁芯存贮器里,静态功耗远远大于动态功耗。提出了用微功耗的CMOS数字电路来代替TTL电路来驱动磁芯负载的设想。通过1K×16位磁芯存贮器的实践,磁芯存贮器的耗功完全能降下来,在存取周期为8μs时,耗功3w。 This article describes the issues related to reducing core memory consumption. Analysis of the core memory consumption of the distribution. Static memory consumes much more power than dynamic in core memory with unpleasant access cycles. Proposed to use micro-power CMOS digital circuit to replace the TTL circuit to drive the load of the core idea. Through the practice of 1K × 16-bit magnetic memory, the power consumption of magnetic memory can be reduced completely, consuming 3w when the access cycle is 8μs.