For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array(FPGA), a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit(IC)design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip. For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array (FPGA), a low-power consumption design method is proposed, which is suitable for FPGA implementation. ) design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will be lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.