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This paper presents a 10Gb/s high-speed equalizer as the front-end of a receiver for backplane communication.The equalizer combines an analog equalizer and a two-tap decision-feedback equalizer in a half-rate structure to reduce the inter-symbol-interference(ISI) of the communication channel.By employing inductive peaking technique for the high-frequency boost circuit,the bandwidth and the boost of the analog equalizer are improved.The decision-feedback equalizer optimizes the size of the CML-based circuit such as D flip-flops(DFF) and multiplex(MUX),shortening the feedback path delay and speeding up the operation considerably.Designed in the 0.18μm CMOS technology,the equalizer delivers 10Gb/s data over 18-in FR4 trace with 28-dB loss while drawing27-mW from a 1.8-V supply.The overall chip area including pads is 0.6×0.7mm~2.
This paper presents a 10Gb / s high-speed equalizer as the front-end of a receiver for backplane communication. The equalizer combines an analog equalizer and a two-tap decision-feedback equalizer in a half-rate structure to reduce the inter-symbol -interference (ISI) of the communication channel.By employing inductive peaking technique for the high-frequency boost circuit, the bandwidth and the boost of the analog equalizer are improved.The decision-feedback equalizer optimizes the size of the CML-based circuit such as D flip-flops (DFF) and multiplex (MUX), shortening the feedback path delay and speeding up the operation. In. 0.18 μm CMOS technology, the equalizer delivers 10Gb / s data over 18-in FR4 trace with 28- dB loss while drawing27-mW from a 1.8-V supply.The overall chip area including pads is 0.6 × 0.7mm ~ 2.