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本文对 L=0.55μm LDD MOSFET’s的杂质分布及侧墙工艺进行了研究,提出了亚微米 LDD MOSFET’s集成电路的优化工艺设计.
In this paper, the impurity distribution of L = 0.55μm LDD MOSFET’s and the sidewall technology are studied, and the optimized process design of submicron LDD MOSFET’s integrated circuit is proposed.