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硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSV RC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45 nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSV RC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能.
TSV is a mainstream technology of 3D integrated circuits.According to TSV parasitic parameter extraction model, TSV resistance-capacitance (RC) parameters of different physical dimensions are extracted, and the model accuracy is verified by Q3D simulation results.Analysis of TSV RC effect on the performance and power consumption of the system-on-chip, an analytical model of the delay and power consumption of the three-dimensional interconnects inserted in the buffer is derived.With the 45 nm CMOS process, different sizes of interconnects The simulation results show that the TSV RC effect leads to an average increase of 10% in the interconnection delay and an average increase of 21% in the power density of the interconnects, and the smaller the scale of the circuit is, the more significant the TSV effect is.In the front-end design of a three-dimensional system, The TSV parasitic interconnect model will help designers predict more accurately the performance of on-chip interconnects.