本文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出双边沿触发器的设计思想与基于与非门的逻辑设计．用ＰＳＰＩＣＥ程序模拟证实了该种触发器具有正确的逻辑功能，能够正常地应用于时序电路的设计，并且由于时钟工作频率减半而导致系统功耗的明显降低． In this paper, starting from the requirement of eliminating the ineffective power dissipation caused by the redundant transition of clock signal, the design idea of ​​double-edge-triggered flip-flop and the logic design based on NAND gate are proposed. The simulation with PSPICE proves that the flip-flop has the correct logic function and can be normally applied to the design of a sequential circuit, and the power consumption of the system is significantly reduced due to the halving of the clock operating frequency.