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基于S模式数据链技术的广播式自动相关监视(ADS-B)系统,凭借其建设成本低及其精度高的优点而广泛用于空中交通管制等领域。然而,ADS-B系统的广播性和信号非加密特点,在高A/C应答异步干扰(FRUIT)交叠的情况下,使得信号在接收端被接收时极易产生误码。针对这一问题,结合FPGA的并行运算特性与资源配置情况,在循环冗余编码(CRC)校验和置信度判定的基础上,提出了一种基于FPGA的改进ADS-B纠错算法。给出了该改进算法的设计方案,并通过FPGA平台进行了大量实采信号的测试验证。经多次测试的结果表明:在不影响纠错性能的条件下,该改进算法可节省硬件开销,提升信号处理速度,保证了信号传输的可靠性。
The ADS-B system based on S-mode data link technology is widely used in air traffic control and other fields due to its low construction cost and high precision. However, the broadcast and signal non-encryption characteristics of the ADS-B system make it extremely susceptible to error when the signal is received at the receiving end, in the case of high A / C-response asynchronous interference (FRUIT) overlap. To solve this problem, an improved ADS-B error correction algorithm based on FPGA is proposed based on the parallel computing features and resource allocation of the FPGA based on the cyclic redundancy check (CRC) and the confidence decision. The design scheme of the improved algorithm is given, and a lot of real signals are verified by FPGA platform. The test results show that the improved algorithm can save the hardware overhead, improve the signal processing speed and ensure the reliability of signal transmission without affecting the performance of error correction.