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基于电子不停车收费系统(ETC)接收机的要求,在TSMC018μm工艺下设计并实现一种8bit 32 MS/s流水线型模数转换器。通过详细理论分析确定设计参数和电路模型,通过运放共享以及带有增益自举的套筒式运算放大器和开关电容共模反馈电路降低电路的静态功耗,通过动态比较器以及静态锁存结构降低电路的动态功耗,使得功耗降低为原来的一半。测试结果显示ADC输入摆幅-0.4~0.4V下,功耗5.017mA,非使能状态下功耗0.567μA,信噪比(SNR)49.21dB,有效位(ENOB)7.77bit,无杂散噪声(SFDR)65.41dB,面积580μm×450μm。
Based on the requirements of ETC receiver, an 8bit 32 MS / s pipeline A / D converter is designed and implemented in TSMC018μm process. Through detailed theoretical analysis to determine the design parameters and circuit model, through the op amp share and gain bootstrap sleeve op amp and switched capacitor common mode feedback circuit to reduce the static power consumption of the circuit, through the dynamic comparator and static latch structure Reduce the dynamic power of the circuit, making the power consumption reduced to half the original. The test results show that the ADC input swing is -0.4 ~ 0.4V, the power consumption is 5.017mA, the power consumption is 0.567μA in non-enabled state, the SNR is 49.21dB, the effective bit (ENOB) is 7.77bit and the spurious noise (SFDR) 65.41dB, area 580μm × 450μm.