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本文主要讨论了小型的同步时序逻辑电路设计时的状态化简问题,并给出确定等价状态的一般方法。这种方法具有普遍性,在教学中易于学生接受和掌握。
This paper mainly discusses the problem of state simplification in the design of a small synchronous logic circuit, and gives a general method to determine the equivalent state. This method is universal, easy to accept and master in teaching.