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该发明是在同一基底上形成数个 PNP 和NPN 型相反导电类型的晶体管集成电路的制造方法。采用原来的多重扩散法要获得所需形状的结面是有困难的,且做出的上述元件有 VCE特性很高等缺点。该发明采用了一种掩蔽外延技术,从而消除了上述缺点,如下图所示,首先在 P 型基底10上用气相生长法形成一层作掩蔽用的 SiO_2 膜12,然后在其上开矩形孔。再用外延生长法在该孔中形成一个 N 型的岛14,为了降低该岛的固有阻抗,在岛14的表面设置N~+ 埋层。接着再在该片上形成一层 SiO_2 膜30(图
This invention is a method of manufacturing a transistor integrated circuit having a plurality of PNP and NPN opposite conductivity types on the same substrate. Using the original multi-diffusion method to obtain the desired shape of the junction is difficult, and make the above-mentioned components have VCE characteristics such as high shortcomings. The invention uses a masking epitaxy technique to eliminate the above drawbacks. As shown in the following figure, a SiO 2 film 12 for masking is first formed on a P-type substrate 10 by vapor phase growth and then a rectangular hole . Then an epitaxial growth method is used to form an N-type island 14 in the hole. In order to reduce the intrinsic impedance of the island, an N ~ + buried layer is arranged on the surface of the island 14. Then a layer of SiO 2 film 30 is formed on the sheet (Fig