介绍了一种用于12 bit,20 MS/s流水线模数转换器前端的高性能采样/保持电路。该电路采用全差分结构、底极板采样来消除电荷注入和时钟馈通误差。采用栅压自举开关,并通过对电路中的开关进行组合优化,极大地提高了电路的线性性能。同时,运算放大器采用折叠式增益增强结构,以获得较高的增益和带宽。采用CSMC公司的0.5μm CMOS工艺库,对电路进行了仿真和流片。结果表明,在5 V电源电压下,采样频率为20 MHz,采样精度可达到0.012%,在输入信号为奈奎斯特频率时,无杂散动态范围(SFDR)为76 dB。 A high performance sample / hold circuit for the front end of a 12 bit, 20 MS / s pipelined ADC is presented. The circuit uses a fully differential structure, bottom plate sampling to eliminate charge injection and clock feedthrough error. The use of gate voltage bootstrap switch, and through the combination of the circuit switch optimization, which greatly improves the linearity of the circuit. At the same time, the op amp uses a folded gain enhancement structure for high gain and bandwidth. Using CSMC’s 0.5μm CMOS technology library, the circuit simulation and flow sheet. The results show that at a 5 V supply voltage, the sampling frequency is 20 MHz and the sampling accuracy can reach 0.012%, with an SFDR of 76 dB at the input signal’s Nyquist frequency.