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本文提出了一种新的集成注入逻辑结构——集成注入肖特基逻辑(I~2SL)。该结构采用P埋集电极纵向PNP晶体管作注入器,巧妙地实现了与正常向下工作的NPN晶体管并合。实验结果表明:在模拟电路晶体管击穿电压为20～30 V时,I~2SL的门延迟小于15ns,比常规I~2L的小5倍以上。
This paper presents a new integrated injection logic structure - integrated injection Schottky logic (I ~ 2SL). The structure uses P buried collector longitudinal PNP transistor as an injector, cleverly achieved with the normal down NPN transistor work. The experimental results show that the gate delay of I ~ 2SL is less than 15ns when the breakdown voltage of analog transistor is 20 ~ 30V, which is more than 5 times smaller than that of conventional I ~ 2L.