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从六十年代中期的电阻—晶体管逻辑(RCL)电路开始,20年来,标准逻辑电路技术不断发展.在多半时间里,继RTL 之后的高性能双极电路引人注目,但在八十年代,CMOS 技术力争超过双极技术.CMOS 逻辑的HC/HCT 系列揭示了第一次挑战.它提供了与低功耗肖特基TTL(LSTTL)双极逻辑电路差不多相同的性能,但功耗低得多.CMOS 方面的最新进展是Texasinstrument、Philips和Signetios 公司推出的先进CMOS逻辑(Adwanced CMOS Logic—ACL)。ACL 是1μm 逻辑技术,在速度、功耗和驱动能力方面补充高性能的双极逻辑器件的不足.ACL 工艺采用双阱结构,因此可以使晶体管密集排列.由于器件紧密地聚集,内部门元件的开关延迟为亚毫微秒级.这些工艺非常适合于SSI 和MSI 逻辑器件的大量生产.随着芯片技术从分立的逻辑功能转向专用IC,LSI 和VLSI 也将随之转变.为了达到双极逻辑电路的速度,Signetics、TI 和philips开发了一种制作CMOS 晶体管栅和源/(?)区的硅化物工艺。硅化物的好处是它的电阻率低,这导致逻辑元件间互连电阻减小.侧壁氧化工艺形成了硅化物侧面的“补充层”,从而减小了栅/源和漏/源之间的寄生电容的影响.
Since the resistance-transistor logic (RCL) circuit of the mid-1960s, standard logic has evolved over the last two decades, with high-performance bipolar circuits following RTL appearing for most of the time, but in the 1980s, CMOS technology strives to outperform bipolar technology. The CMOS logic HC / HCT family reveals the first challenge. It offers almost the same performance as a low power Schottky TTL (LSTTL) bipolar logic circuit, but with low power consumption The latest advancements in CMOS are advanced CMOS logic (Adwanced CMOS Logic-ACLs) from Texas Instruments, Philips and Signetios. ACL is a 1μm logic technology that complements the high-performance bipolar logic devices in terms of speed, power consumption and drive capability. The ACL process uses a double-well structure that allows transistors to be densely packed. As the devices are tightly packed, the internal gate components Switching delay of sub-nanosecond.These processes are ideal for mass production of SSI and MSI logic devices.As the chip technology from discrete logic functions to dedicated IC, LSI and VLSI will also be changed.To achieve bipolar logic Circuits, Signetics, TI and Philips have developed a silicide process that makes CMOS transistor gates and source / (?) Regions. The benefits of silicide are its low resistivity, which results in a reduction in the resistance of interconnects between logic elements. The sidewall oxidation process forms a “make-up” on the silicide side, reducing gate-to-source and drain-to- The effect of parasitic capacitance.