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随着集成电路线宽不断缩减,现场可编程逻辑的密度不断呈指数增长.目前,10,000门(可用)设计可以方便地纳入单一现场可编程门阵列(FPGA)芯片.这意味着,FPGA设计人员将进入集成系统设计领域,就象ASIC设计人员在80年代中期所做的那样.这一转变要求一种新的设计模式,并把这种转变从门级方法推向高级方法.FPGA设计人员现在面临着同样局面.本文首先探讨FPGA设计突破10,000门大关后所面临的设计问题.然后阐明FPGA设计成功的新模式,以及为这种模式优化的FPGA关键特性.ASIC和FPGA发展趋势随着集成电路线宽不断缩减,加工工艺的定标规则(scaling rules)已使门密度呈指数增加,延迟直线下降.自1985年以来,“标称”ASIC(门阵列和基
As density in integrated circuits shrinks, the density of field programmable logic continues to grow exponentially, and at present, 10,000 (available) designs are easily incorporated into a single Field Programmable Gate Array (FPGA) chip, meaning that FPGA designers Will enter into the field of integrated system design, as ASIC designers did in the mid-1980s, a shift that requires a new design paradigm and move this transition from a gate-level approach to an advanced one. FPGA Designers Now Facing the same situation.First, this article explores the design issues faced by FPGA design after breaking the 10,000 mark.And then illustrates the new model of FPGA design success, as well as the key characteristics of FPGA optimized for this mode.ASIC and FPGA development trend with the integration Scales of circuitry have been shrinking and scaling rules for processing have exponentially increased gate densities with a linearly decreasing delay. Since 1985, “nominal” ASICs (gate array and base