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A design of high dynamic range linear radio frequency power detector(PD),aimed for transmitter carrier leakage suppression is presented in this paper.Based on the logarithmic amplifier principle,this detector utilizes the successive detection method to achieve a high dynamic range in the radio frequency band.In order to increase sensitivity,a low noise amplifier(LNA) is placed in the front of this detector.DC coupling is adopted in this architecture to reduce parasitics and save area.but this will unavoidably cause DC offsets in the circuit which are detrimental to the dynamic range.So a DC offset cancelling(DCOC) technique is proposed to solve the problem.Finally,this detector was fabricated in the SMIC 0.13μm CMOS process.The measured results show that it achieves a wide dynamic range of 50 dB/40 dB with log errors in±1 dB at 900 MHz/2 GHz,while draws 16 mA from a 1.5 V power supply.The active chip area is 0.27 x 0.67 mm~2.
A design of high dynamic range linear radio frequency power detector (PD), aimed at transmitter leakage suppression is presented in this paper. Based on the logarithmic amplifier principle, this detector utilizes the successive detection method to achieve a high dynamic range in the radio frequency band.In order to increase sensitivity, a low noise amplifier (LNA) is placed in the front of this detector. DC coupling is adopted in this architecture to reduce parasitics and save area. but this will unavoidably cause DC offsets in the circuit which are detrimental to the dynamic range. So DC offset canceling (DCOC) technique is proposed to solve the problem. Finally, this detector was fabricated in the SMIC 0.13 μm CMOS process. The measured results show that it achieves a wide dynamic range of 50 dB / 40 dB with log errors in ± 1 dB at 900 MHz / 2 GHz, while draws 16 mA from a 1.5 V power supply. The active chip area is 0.27 x 0.67 mm ~ 2.